Re: OT: kernel in C? how translated? [Was Re: Help]

From: Ron Johnson (ron.l.johnson_at_cox.net)
Date: 12/12/04

  • Next message: Steve Lamb: "Re: Hardlinks to remote directories"
    To: Debian-User <debian-user@lists.debian.org>
    Date: Sat, 11 Dec 2004 21:11:50 -0600
    
    
    

    On Sat, 2004-12-11 at 10:51 -0500, William Ballard wrote:
    > On Sat, Dec 11, 2004 at 09:39:51AM -0600, Kent West wrote:
    > > The kernel is the core of the operating system. The operating system is
    > > composed of the kernel and any utilities that ride on top of that
    > > kernel. Debian/GNU Linux is a GNU operating system using the Linux kernel.
    >
    > Today's CPUs are actually an operating system unto themselves. Each
    > machine code instruction is broken into multiple microcode instructions.
    > The CPU exposes certain services which the "userland" :-) (i.e., ring 0)
    > code sitting on top of it consumes.

    Actually, it's been that way for 30ish years. That's what CISC is.
    Examples of such designs are the PDP-11, VAX, MC68K and, of course,
    the 8086. The "CPU" at the heart of the IBM 360/370/390 mainframes
    was also very CISC.

    The microcode of the VAX and mainframes was loaded from a floppy
    drive at IPL (that's the mainframe term for boot: Initial Program
    Load). In fact, on the VAX, you could (and many shops did!) alter
    the functionality of certain opcodes. Say you were writing a
    scientific app in assembly (the VAX makes it *really* easy to code
    in assembly) that didn't need Packed Decimal operations, but did
    need some other function "foo". If you were a High Wizard of VAX,
    you'd write foo directly in microcode. Very cool.

    VAX instructions were designed to make it *very* easy to compile
    FORTRAN and COBOL.

    Unfortunately, CISC doesn't scale as well in the raw speed department.
    That's where RISC comes in: few instructions, lots of registers, no
    microcode, all instructions hard-wired into silicon. Bad for assembly
    programmers, good for compiler writers and CPU designers.

    Ever since the Pentium and the AMD/NexGen K5, x86 CPUs have been
    RISC inside, with translation circuitry to convert the CISC opcodes
    into "internal micro opcodes".

    (The extra translation circuitry is what causes x86 CPUs to run
    extra hot, compared to POWER, Alpha and SPARC, since the extra
    transistors need electricity, too.)

    -- 
    -----------------------------------------------------------------
    Ron Johnson, Jr.
    Jefferson, LA USA
    PGP Key ID 8834C06B I prefer encrypted mail.
    NAMBLA - Nat'l Assoc of Marlon Brando Look-Alikes (Yes, it's a
    South Park reference.)
    
    

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