RE: Problems related to DMA or DDR memory on Intel 845 chipset?

From: Kathy Frazier (kfrazier_at_mdc-dayton.com)
Date: 07/28/03

  • Next message: David S. Miller: "Re: The Well-Factored 386"
    To: <linux-kernel@vger.kernel.org>, "Mark Hahn" <hahn@physics.mcmaster.ca>
    Date:	Mon, 28 Jul 2003 16:56:42 -0500
    
    

    Mark,

    >> then "hang". I had discovered that upon this failure, the logic analyzer
    >> shows that our device is asserting the interrupt. However, I also found
    (by
    >> adding my own debug to the kernel) that the 8259 Programmable Interrupt
    >> Controller never received the interrupt (it's bit was not set in the

    >OK, so the problem is strictly on the PCI bus, between your device
    >and the PIC (or apic?)

    That would appear to be the case. But as I said, it appears to be a nasty
    side affect from something that has gone wrong during a DMA transfer. BTW,
    we are using PIC

    >> interrupt on the device). At this point of failure, no other IRQs are
    >> getting through, so the system appears to be completely hard hung even
    >> though various software components are still running. We are operating
    in a

    >so why do you think this is a software problem?

    I made this posting to see if anyone else has had problems with this
    hardware or to see if there were any known issues similar to what I've
    found.

    >> employs the DDR memory technology) running Linux 2.4.20-8. Further
    testing
    >> has shown that "not receiving an interrupt" is just a nasty side affect
    from
    >> something that has gone wrong during a DMA transfer by our device. This
    was
    >> discovered when I changed the driver to poll for a DMA completion rather
    >> than have it interrupt me. Our system still hung. We are have tried

    >that one mystifies me: how do you conclude the problem is a broken
    >DMA transfer if, when you convert to polling, the problem remains?

    Why? The device is _still_ a DMA device. In this particular test I told it
    to initiate the DMA, but I did not enable it's ability to interrupt me when
    it was finished with the DMA. I poll to watch for it's completion.

    >my conclusion would be that your device has somehow managed to lock
    >up the PIC's state-machine, or is somehow playing nasty with the bus.

    I haven't ruled that out.

    . . . Meanwhile, I made another discovery on the internet that indicates
    that DMA is not supported with an ICH4 controller (which is what this system
    has) until Linux version 2.5.12 (we're using 2.4.20-8). See:
    http://64.143.3.64/downloads/drivers/845/perform/linux/udma.htm. I posted a
    question concerning this to linux-kernel. See thread: DMA not supported
    with Intel ICH4 I/O controller? Unfortunately, I have not received any
    response that supports or refutes this. Any thoughts?

    Thanks,
    Kathy

    -
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to majordomo@vger.kernel.org
    More majordomo info at http://vger.kernel.org/majordomo-info.html
    Please read the FAQ at http://www.tux.org/lkml/


  • Next message: David S. Miller: "Re: The Well-Factored 386"

    Relevant Pages

    • Re: Handling high UDP throughput
      ... The product that uses this sustains 540MbS with a 38kHz interrupt running using more than half the processor's power, so a lot goes on in the system but a lot of time is available for TCP/IP. ... The Ethernet driver was optimized, the memory movement was optimized (just using an inline memcpy that does a DMA transfer adds 30% to the effective speed), the IP checksum was in assembly, and a zero-copy TCP/IP stack was required. ... How much TX buffers did you have? ...
      (comp.arch.embedded)
    • Re: TL16C550CIFN
      ... verify this UART's DMA function,but the /RXRDY goes true when there is ... IIRC most cacheing UARTs will allow you to adjust the trigger point ... Thus once an interrupt occurs the service can ... or more characters in the FIFO and more than three character ...
      (comp.arch.embedded)
    • Re: TL16C550CIFN
      ... want to know why and can u give me a example of DMA mode configuration. ... IIRC most cacheing UARTs will allow you to adjust the trigger point ... Thus once an interrupt occurs the service can ... not when the rxbuffer reach the trigger. ...
      (comp.arch.embedded)
    • Re: TL16C550CIFN
      ... verify this UART's DMA function,but the /RXRDY goes true when there is ... IIRC most cacheing UARTs will allow you to adjust the trigger point ... Thus once an interrupt occurs the service can ... or more characters in the FIFO and more than three character ...
      (comp.arch.embedded)
    • Re: Windows Explorer slow to respond
      ... report, below, as I'm still not sure whether my machine is using DMA or PIO. ... IDE Controller: Intel82801DB Ultra ATA Controller, ... DMA MW Mode Support: 1 - 2 ... Default Transfer Mode: UDMA-5 ...
      (microsoft.public.windowsxp.general)