Re: [PATCH] Athlon Prefetch workaround for 2.6.0test6
From: Nick Piggin (piggin_at_cyberone.com.au)
Date: 09/30/03
- Previous message: Rick Lindsley: "Scheduling latency summary"
- In reply to: bill davidsen: "Re: [PATCH] Athlon Prefetch workaround for 2.6.0test6"
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Date: Tue, 30 Sep 2003 10:50:57 +1000 To: bill davidsen <davidsen@tmr.com>
bill davidsen wrote:
>In article <20030929125629.GA1746@averell>, Andi Kleen <ak@muc.de> wrote:
>
>| It removes the previous dumb in kernel workaround for this and shrinks the
>| kernel by >10k.
>|
>| Small behaviour change is that a SIGBUS fault for a *_user access will
>| cause an EFAULT now, no SIGBUS.
>|
>| This version addresses all criticism that I got for previous versions.
>|
>| - Only checks on AMD K7+ CPUs.
>| - Computes linear address for VM86 mode or code segments
>| with non zero base.
>| - Some cleanup
>| - No pointer comparisons
>| - More comments
>
>I have to try this on a P4 and K7, but WRT "Only checks on AMD K7+ CPUs"
>I hope you meant "only generates code if AMD CPU is target" and not that
>the code size penalty is still there for CPUs which don't need it.
>
>Will check Wednesday, life is very busy right now.
>
No, the code is not conditionally compiled. That is a different issue to
this patch though. The target CPU selection scheme doesn't work at all
like you would expect and its impossible to compile this sort of code
out (when on x86 arch). See Adrian's code to rationalise cpu selection.
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- Previous message: Rick Lindsley: "Scheduling latency summary"
- In reply to: bill davidsen: "Re: [PATCH] Athlon Prefetch workaround for 2.6.0test6"
- Next in thread: Dave Jones: "Re: [PATCH] Athlon Prefetch workaround for 2.6.0test6"
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