TGA fbdev patch.
From: James Simmons (jsimmons_at_infradead.org)
Date: 02/20/04
- Previous message: David Woodhouse: "[PATCH] Fix ISDN v.110."
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Date: Fri, 20 Feb 2004 18:29:09 +0000 (GMT) To: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Please try this patch against the latest kernel. If it works for people
let me know so I can pass it to linus.
diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/logo/Kconfig fbdev-2.6/drivers/video/logo/Kconfig
--- linus-2.6/drivers/video/logo/Kconfig 2004-02-18 20:59:12.000000000 -0800
+++ fbdev-2.6/drivers/video/logo/Kconfig 2004-02-18 20:10:03.000000000 -0800
@@ -25,7 +25,7 @@
config LOGO_DEC_CLUT224
bool "224-color Digital Equipment Corporation Linux logo"
- depends on LOGO && DECSTATION
+ depends on LOGO && (DECSTATION || ALPHA)
default y
config LOGO_MAC_CLUT224
diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/logo/logo.c fbdev-2.6/drivers/video/logo/logo.c
--- linus-2.6/drivers/video/logo/logo.c 2004-02-18 20:59:12.000000000 -0800
+++ fbdev-2.6/drivers/video/logo/logo.c 2004-02-18 20:10:04.000000000 -0800
@@ -65,9 +65,14 @@
logo = &logo_linux_clut224;
#endif
#ifdef CONFIG_LOGO_DEC_CLUT224
+# if defined(CONFIG_MIPS) || defined(CONFIG_MIPS64)
/* DEC Linux logo on MIPS/MIPS64 */
if (mips_machgroup == MACH_GROUP_DEC)
logo = &logo_dec_clut224;
+# else
+ /* Assume DEC Linux logo on ALPHA */
+ logo = &logo_dec_clut224;
+# endif
#endif
#ifdef CONFIG_LOGO_MAC_CLUT224
/* Macintosh Linux logo on m68k */
diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/tgafb.c fbdev-2.6/drivers/video/tgafb.c
--- linus-2.6/drivers/video/tgafb.c 2004-02-18 20:59:10.000000000 -0800
+++ fbdev-2.6/drivers/video/tgafb.c 2004-02-18 20:53:34.000000000 -0800
@@ -24,7 +24,7 @@
#include <linux/fb.h>
#include <linux/pci.h>
#include <asm/io.h>
-#include <video/tgafb.h>
+#include <video/tga.h>
/*
* Local functions.
@@ -41,6 +41,7 @@
static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
+static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
#ifdef MODULE
@@ -49,7 +50,6 @@
static const char *mode_option = "640x480@60";
-
/*
* Frame buffer operations
*/
@@ -60,6 +60,7 @@
.fb_set_par = tgafb_set_par,
.fb_setcolreg = tgafb_setcolreg,
.fb_blank = tgafb_blank,
+ .fb_pan_display = tgafb_pan_display,
.fb_fillrect = tgafb_fillrect,
.fb_copyarea = tgafb_copyarea,
.fb_imageblit = tgafb_imageblit,
@@ -127,10 +128,10 @@
tgafb_set_par(struct fb_info *info)
{
static unsigned int const deep_presets[4] = {
- 0x00014000,
- 0x0001440d,
+ 0x00004000,
+ 0x0000440d,
0xffffffff,
- 0x0001441d
+ 0x0000441d
};
static unsigned int const rasterop_presets[4] = {
0x00000003,
@@ -154,7 +155,7 @@
struct tga_par *par = (struct tga_par *) info->par;
u32 htimings, vtimings, pll_freq;
u8 tga_type;
- int i, j;
+ int i;
/* Encode video timings. */
htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
@@ -192,7 +193,8 @@
while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
continue;
mb();
- TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
+ TGA_WRITE_REG(par, deep_presets[tga_type] |
+ (par->sync_on_green ? 0x0 : 0x00010000), TGA_DEEP_REG);
while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
continue;
mb();
@@ -225,37 +227,13 @@
BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
- /* Fill palette registers. */
- BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
- TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
-
- for (i = 0; i < 16; i++) {
- j = color_table[i];
- TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- }
- for (i = 0; i < 240*3; i += 4) {
- TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
- TGA_RAMDAC_REG);
- }
-
} else { /* 24-plane or 24plusZ */
/* Init BT463 registers. */
BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
- (par->sync_on_green ? 0x80 : 0x40));
+ (par->sync_on_green ? 0xc0 : 0x40));
BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
@@ -267,30 +245,6 @@
BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
- /* Fill the palette. */
- BT463_LOAD_ADDR(par, 0x0000);
- TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
-
- for (i = 0; i < 16; i++) {
- j = color_table[i];
- TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- }
- for (i = 0; i < 512*3; i += 4) {
- TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
- TGA_RAMDAC_REG);
- }
-
/* Fill window type table after start of vertical retrace. */
while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
continue;
@@ -314,6 +268,9 @@
}
+ /* Init the palette. */
+ fb_set_cmap(fb_default_cmap(16), 1, info);
+
/* Finally, enable video scan (and pray for the monitor... :-) */
TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
@@ -509,16 +466,8 @@
* Acceleration.
*/
-/**
- * tgafb_imageblit - REQUIRED function. Can use generic routines if
- * non acclerated hardware and packed pixel based.
- * Copies a image from system memory to the screen.
- *
- * @info: frame buffer structure that represents a single frame buffer
- * @image: structure defining the image.
- */
static void
-tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
+tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
{
static unsigned char const bitrev[256] = {
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
@@ -562,6 +511,17 @@
const unsigned char *data;
void *regs_base, *fb_base;
+ is8bpp = info->var.bits_per_pixel == 8;
+
+ /* For copies that aren't pixel expansion, there's little we
+ can do better than the generic code. */
+ /* ??? There is a DMA write mode; I wonder if that could be
+ made to pull the data from the image buffer... */
+ if (image->depth > 1) {
+ cfb_imageblit(info, image);
+ return;
+ }
+
dx = image->dx;
dy = image->dy;
width = image->width;
@@ -579,18 +539,8 @@
if (dy + height > vyres)
height = vyres - dy;
- /* For copies that aren't pixel expansion, there's little we
- can do better than the generic code. */
- /* ??? There is a DMA write mode; I wonder if that could be
- made to pull the data from the image buffer... */
- if (image->depth > 1) {
- cfb_imageblit(info, image);
- return;
- }
-
regs_base = par->tga_regs_base;
fb_base = par->tga_fb_base;
- is8bpp = info->var.bits_per_pixel == 8;
/* Expand the color values to fill 32-bits. */
/* ??? Would be nice to notice colour changes elsewhere, so
@@ -768,6 +718,86 @@
regs_base + TGA_MODE_REG);
}
+static void
+tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+ struct tga_par *par = (struct tga_par *) info->par;
+ u32 color, dx, dy, width, height, vxres, vyres;
+ u32 *palette = ((u32 *)info->pseudo_palette);
+ unsigned long pos, line_length;
+ unsigned long i, j;
+ const unsigned char *data;
+ void *regs_base, *fb_base;
+
+ dx = image->dx;
+ dy = image->dy;
+ width = image->width;
+ height = image->height;
+ vxres = info->var.xres_virtual;
+ vyres = info->var.yres_virtual;
+ line_length = info->fix.line_length;
+
+ /* Crop the image to the screen. */
+ if (dx > vxres || dy > vyres)
+ return;
+ if (dx + width > vxres)
+ width = vxres - dx;
+ if (dy + height > vyres)
+ height = vyres - dy;
+
+ regs_base = par->tga_regs_base;
+ fb_base = par->tga_fb_base;
+
+ pos = dy * line_length + (dx * 4);
+ data = image->data;
+
+ /* Now copy the image, color_expanding via the palette. */
+ for (i = 0; i < height; i++) {
+ for (j = 0; j < width; j++) {
+ color = palette[*data++];
+ __raw_writel(color, fb_base + pos + j*4);
+ }
+ pos += line_length;
+ }
+}
+
+/**
+ * tgafb_imageblit - REQUIRED function. Can use generic routines if
+ * non acclerated hardware and packed pixel based.
+ * Copies a image from system memory to the screen.
+ *
+ * @info: frame buffer structure that represents a single frame buffer
+ * @image: structure defining the image.
+ */
+static void
+tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+ unsigned int is8bpp = info->var.bits_per_pixel == 8;
+
+ /* If a mono image, regardless of FB depth, go do it. */
+ if (image->depth == 1) {
+ tgafb_mono_imageblit(info, image);
+ return;
+ }
+
+ /* For copies that aren't pixel expansion, there's little we
+ can do better than the generic code. */
+ /* ??? There is a DMA write mode; I wonder if that could be
+ made to pull the data from the image buffer... */
+ if (image->depth == info->var.bits_per_pixel) {
+ cfb_imageblit(info, image);
+ return;
+ }
+
+ /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
+ if (!is8bpp && image->depth == 8) {
+ tgafb_clut_imageblit(info, image);
+ return;
+ }
+
+ /* Silently return... */
+}
+
/**
* tgafb_fillrect - REQUIRED function. Can use generic routines if
* non acclerated hardware and packed pixel based.
@@ -1360,6 +1390,31 @@
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_DEC_TGA;
+
+ /*
+ * These are needed by fb_set_logo_truepalette(), so we
+ * set them here for 24-plane cards.
+ */
+ if (tga_type != TGA_TYPE_8PLANE) {
+ info->var.red.length = 8;
+ info->var.green.length = 8;
+ info->var.blue.length = 8;
+ info->var.red.offset = 16;
+ info->var.green.offset = 8;
+ info->var.blue.offset = 0;
+ }
+}
+
+static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ /* We just use this to catch switches out of
+ * graphics mode.
+ */
+ tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
+
+ if (var->xoffset || var->yoffset || var->vmode)
+ return -EINVAL;
+ return 0;
}
static __devinit int
@@ -1371,15 +1426,10 @@
0xffffffff,
TGA_24PLUSZ_FB_OFFSET
};
-
- struct all_info {
- struct fb_info info;
- struct tga_par par;
- u32 pseudo_palette[16];
- } *all;
-
- void *mem_base;
unsigned long bar0_start, bar0_len;
+ struct fb_info *info;
+ struct tga_par *par;
+ void *mem_base;
u8 tga_type;
int ret;
@@ -1390,13 +1440,12 @@
}
/* Allocate the fb and par structures. */
- all = kmalloc(sizeof(*all), GFP_KERNEL);
- if (!all) {
+ info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev);
+ if (!info) {
printk(KERN_ERR "tgafb: Cannot allocate memory\n");
return -ENOMEM;
}
- memset(all, 0, sizeof(*all));
- pci_set_drvdata(pdev, all);
+ pci_set_drvdata(pdev, info);
/* Request the mem regions. */
bar0_start = pci_resource_start(pdev, 0);
@@ -1416,24 +1465,22 @@
/* Grab info about the card. */
tga_type = (readl(mem_base) >> 12) & 0x0f;
- all->par.pdev = pdev;
- all->par.tga_mem_base = mem_base;
- all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
- all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
- all->par.tga_type = tga_type;
- pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
+ par = info->par;
+ par->tga_mem_base = mem_base;
+ par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
+ par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
+ par->tga_type = tga_type;
+ pci_read_config_byte(pdev, PCI_REVISION_ID, par->tga_chip_rev);
/* Setup framebuffer. */
- all->info.flags = FBINFO_FLAG_DEFAULT;
- all->info.fbops = &tgafb_ops;
- all->info.screen_base = (char *) all->par.tga_fb_base;
- all->info.currcon = -1;
- all->info.par = &all->par;
- all->info.pseudo_palette = all->pseudo_palette;
+ info->flags = FBINFO_FLAG_DEFAULT;
+ info->fbops = &tgafb_ops;
+ info->screen_base = (char *) par->tga_fb_base;
+ info->pseudo_palette = par->pseudo_palette;
/* This should give a reasonable default video mode. */
- ret = fb_find_mode(&all->info.var, &all->info, mode_option,
+ ret = fb_find_mode(&info->var, info, mode_option,
NULL, 0, NULL,
tga_type == TGA_TYPE_8PLANE ? 8 : 32);
if (ret == 0 || ret == 4) {
@@ -1442,35 +1489,34 @@
goto err1;
}
- if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
+ if (fb_alloc_cmap(&info->cmap, 256, 0)) {
printk(KERN_ERR "tgafb: Could not allocate color map\n");
ret = -ENOMEM;
goto err1;
}
- tgafb_set_par(&all->info);
- tgafb_init_fix(&all->info);
+ tgafb_init_fix(info);
- if (register_framebuffer(&all->info) < 0) {
+ if (register_framebuffer(info) < 0) {
printk(KERN_ERR "tgafb: Could not register framebuffer\n");
ret = -EINVAL;
goto err1;
}
printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
- all->par.tga_chip_rev);
+ par->tga_chip_rev);
printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
pdev->bus->number, PCI_SLOT(pdev->devfn),
PCI_FUNC(pdev->devfn));
printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
- all->info.node, all->info.fix.id, bar0_start);
+ info->node, info->fix.id, bar0_start);
return 0;
err1:
release_mem_region(bar0_start, bar0_len);
err0:
- kfree(all);
+ framebuffer_release(info);
return ret;
}
@@ -1493,7 +1539,7 @@
iounmap(par->tga_mem_base);
release_mem_region(pci_resource_start(pdev, 0),
pci_resource_len(pdev, 0));
- kfree(info);
+ framebuffer_release(info);
}
static void __exit
diff -urN -X /home/jsimmons/dontdiff linus-2.6/include/video/tga.h fbdev-2.6/include/video/tga.h
--- linus-2.6/include/video/tga.h 1969-12-31 16:00:00.000000000 -0800
+++ fbdev-2.6/include/video/tga.h 2004-02-18 20:53:12.000000000 -0800
@@ -0,0 +1,241 @@
+/*
+ * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
+ *
+ * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
+ *
+ * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#ifndef TGAFB_H
+#define TGAFB_H
+
+/*
+ * TGA hardware description (minimal)
+ */
+
+#define TGA_TYPE_8PLANE 0
+#define TGA_TYPE_24PLANE 1
+#define TGA_TYPE_24PLUSZ 3
+
+/*
+ * Offsets within Memory Space
+ */
+
+#define TGA_ROM_OFFSET 0x0000000
+#define TGA_REGS_OFFSET 0x0100000
+#define TGA_8PLANE_FB_OFFSET 0x0200000
+#define TGA_24PLANE_FB_OFFSET 0x0804000
+#define TGA_24PLUSZ_FB_OFFSET 0x1004000
+
+#define TGA_FOREGROUND_REG 0x0020
+#define TGA_BACKGROUND_REG 0x0024
+#define TGA_PLANEMASK_REG 0x0028
+#define TGA_PIXELMASK_ONESHOT_REG 0x002c
+#define TGA_MODE_REG 0x0030
+#define TGA_RASTEROP_REG 0x0034
+#define TGA_PIXELSHIFT_REG 0x0038
+#define TGA_DEEP_REG 0x0050
+#define TGA_PIXELMASK_REG 0x005c
+#define TGA_CURSOR_BASE_REG 0x0060
+#define TGA_HORIZ_REG 0x0064
+#define TGA_VERT_REG 0x0068
+#define TGA_BASE_ADDR_REG 0x006c
+#define TGA_VALID_REG 0x0070
+#define TGA_CURSOR_XY_REG 0x0074
+#define TGA_INTR_STAT_REG 0x007c
+#define TGA_DATA_REG 0x0080
+#define TGA_RAMDAC_SETUP_REG 0x00c0
+#define TGA_BLOCK_COLOR0_REG 0x0140
+#define TGA_BLOCK_COLOR1_REG 0x0144
+#define TGA_BLOCK_COLOR2_REG 0x0148
+#define TGA_BLOCK_COLOR3_REG 0x014c
+#define TGA_BLOCK_COLOR4_REG 0x0150
+#define TGA_BLOCK_COLOR5_REG 0x0154
+#define TGA_BLOCK_COLOR6_REG 0x0158
+#define TGA_BLOCK_COLOR7_REG 0x015c
+#define TGA_COPY64_SRC 0x0160
+#define TGA_COPY64_DST 0x0164
+#define TGA_CLOCK_REG 0x01e8
+#define TGA_RAMDAC_REG 0x01f0
+#define TGA_CMD_STAT_REG 0x01f8
+
+
+/*
+ * Useful defines for managing the registers
+ */
+
+#define TGA_HORIZ_ODD 0x80000000
+#define TGA_HORIZ_POLARITY 0x40000000
+#define TGA_HORIZ_ACT_MSB 0x30000000
+#define TGA_HORIZ_BP 0x0fe00000
+#define TGA_HORIZ_SYNC 0x001fc000
+#define TGA_HORIZ_FP 0x00007c00
+#define TGA_HORIZ_ACT_LSB 0x000001ff
+
+#define TGA_VERT_SE 0x80000000
+#define TGA_VERT_POLARITY 0x40000000
+#define TGA_VERT_RESERVED 0x30000000
+#define TGA_VERT_BP 0x0fc00000
+#define TGA_VERT_SYNC 0x003f0000
+#define TGA_VERT_FP 0x0000f800
+#define TGA_VERT_ACTIVE 0x000007ff
+
+#define TGA_VALID_VIDEO 0x01
+#define TGA_VALID_BLANK 0x02
+#define TGA_VALID_CURSOR 0x04
+
+#define TGA_MODE_SBM_8BPP 0x000
+#define TGA_MODE_SBM_24BPP 0x300
+
+#define TGA_MODE_SIMPLE 0x00
+#define TGA_MODE_SIMPLEZ 0x10
+#define TGA_MODE_OPAQUE_STIPPLE 0x01
+#define TGA_MODE_OPAQUE_FILL 0x21
+#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
+#define TGA_MODE_TRANSPARENT_FILL 0x23
+#define TGA_MODE_BLOCK_STIPPLE 0x0d
+#define TGA_MODE_BLOCK_FILL 0x2d
+#define TGA_MODE_COPY 0x07
+#define TGA_MODE_DMA_READ_COPY_ND 0x17
+#define TGA_MODE_DMA_READ_COPY_D 0x37
+#define TGA_MODE_DMA_WRITE_COPY 0x1f
+
+
+/*
+ * Useful defines for managing the ICS1562 PLL clock
+ */
+
+#define TGA_PLL_BASE_FREQ 14318 /* .18 */
+#define TGA_PLL_MAX_FREQ 230000
+
+
+/*
+ * Useful defines for managing the BT485 on the 8-plane TGA
+ */
+
+#define BT485_READ_BIT 0x01
+#define BT485_WRITE_BIT 0x00
+
+#define BT485_ADDR_PAL_WRITE 0x00
+#define BT485_DATA_PAL 0x02
+#define BT485_PIXEL_MASK 0x04
+#define BT485_ADDR_PAL_READ 0x06
+#define BT485_ADDR_CUR_WRITE 0x08
+#define BT485_DATA_CUR 0x0a
+#define BT485_CMD_0 0x0c
+#define BT485_ADDR_CUR_READ 0x0e
+#define BT485_CMD_1 0x10
+#define BT485_CMD_2 0x12
+#define BT485_STATUS 0x14
+#define BT485_CMD_3 0x14
+#define BT485_CUR_RAM 0x16
+#define BT485_CUR_LOW_X 0x18
+#define BT485_CUR_HIGH_X 0x1a
+#define BT485_CUR_LOW_Y 0x1c
+#define BT485_CUR_HIGH_Y 0x1e
+
+
+/*
+ * Useful defines for managing the BT463 on the 24-plane TGAs
+ */
+
+#define BT463_ADDR_LO 0x0
+#define BT463_ADDR_HI 0x1
+#define BT463_REG_ACC 0x2
+#define BT463_PALETTE 0x3
+
+#define BT463_CUR_CLR_0 0x0100
+#define BT463_CUR_CLR_1 0x0101
+
+#define BT463_CMD_REG_0 0x0201
+#define BT463_CMD_REG_1 0x0202
+#define BT463_CMD_REG_2 0x0203
+
+#define BT463_READ_MASK_0 0x0205
+#define BT463_READ_MASK_1 0x0206
+#define BT463_READ_MASK_2 0x0207
+#define BT463_READ_MASK_3 0x0208
+
+#define BT463_BLINK_MASK_0 0x0209
+#define BT463_BLINK_MASK_1 0x020a
+#define BT463_BLINK_MASK_2 0x020b
+#define BT463_BLINK_MASK_3 0x020c
+
+#define BT463_WINDOW_TYPE_BASE 0x0300
+
+#ifdef __KERNEL__
+
+/*
+ * The framebuffer driver private data.
+ */
+
+struct tga_par {
+ /* PCI device. */
+ struct pci_dev *pdev;
+
+ /* Device dependent information. */
+ void *tga_mem_base;
+ void *tga_fb_base;
+ void *tga_regs_base;
+ u8 tga_type; /* TGA_TYPE_XXX */
+ u8 tga_chip_rev; /* dc21030 revision */
+
+ /* Remember blank mode. */
+ u8 vesa_blanked;
+
+ /* Define the video mode. */
+ u32 xres, yres; /* resolution in pixels */
+ u32 htimings; /* horizontal timing register */
+ u32 vtimings; /* vertical timing register */
+ u32 pll_freq; /* pixclock in mhz */
+ u32 bits_per_pixel; /* bits per pixel */
+ u32 sync_on_green; /* set if sync is on green */
+};
+
+
+/*
+ * Macros for reading/writing TGA and RAMDAC registers
+ */
+
+static inline void
+TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
+{
+ writel(v, par->tga_regs_base +r);
+}
+
+static inline u32
+TGA_READ_REG(struct tga_par *par, u32 r)
+{
+ return readl(par->tga_regs_base +r);
+}
+
+static inline void
+BT485_WRITE(struct tga_par *par, u8 v, u8 r)
+{
+ TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
+}
+
+static inline void
+BT463_LOAD_ADDR(struct tga_par *par, u16 a)
+{
+ TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
+ TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
+}
+
+static inline void
+BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
+{
+ BT463_LOAD_ADDR(par, a);
+ TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
+ TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
+}
+#endif /* __KERNEL__ */
+
+#endif /* TGAFB_H */
diff -urN -X /home/jsimmons/dontdiff linus-2.6/include/video/tgafb.h fbdev-2.6/include/video/tgafb.h
--- linus-2.6/include/video/tgafb.h 2004-02-18 21:01:55.000000000 -0800
+++ fbdev-2.6/include/video/tgafb.h 1969-12-31 16:00:00.000000000 -0800
@@ -1,238 +0,0 @@
-/*
- * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
- *
- * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
- *
- * $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef TGAFB_H
-#define TGAFB_H
-
-/*
- * TGA hardware description (minimal)
- */
-
-#define TGA_TYPE_8PLANE 0
-#define TGA_TYPE_24PLANE 1
-#define TGA_TYPE_24PLUSZ 3
-
-/*
- * Offsets within Memory Space
- */
-
-#define TGA_ROM_OFFSET 0x0000000
-#define TGA_REGS_OFFSET 0x0100000
-#define TGA_8PLANE_FB_OFFSET 0x0200000
-#define TGA_24PLANE_FB_OFFSET 0x0804000
-#define TGA_24PLUSZ_FB_OFFSET 0x1004000
-
-#define TGA_FOREGROUND_REG 0x0020
-#define TGA_BACKGROUND_REG 0x0024
-#define TGA_PLANEMASK_REG 0x0028
-#define TGA_PIXELMASK_ONESHOT_REG 0x002c
-#define TGA_MODE_REG 0x0030
-#define TGA_RASTEROP_REG 0x0034
-#define TGA_PIXELSHIFT_REG 0x0038
-#define TGA_DEEP_REG 0x0050
-#define TGA_PIXELMASK_REG 0x005c
-#define TGA_CURSOR_BASE_REG 0x0060
-#define TGA_HORIZ_REG 0x0064
-#define TGA_VERT_REG 0x0068
-#define TGA_BASE_ADDR_REG 0x006c
-#define TGA_VALID_REG 0x0070
-#define TGA_CURSOR_XY_REG 0x0074
-#define TGA_INTR_STAT_REG 0x007c
-#define TGA_DATA_REG 0x0080
-#define TGA_RAMDAC_SETUP_REG 0x00c0
-#define TGA_BLOCK_COLOR0_REG 0x0140
-#define TGA_BLOCK_COLOR1_REG 0x0144
-#define TGA_BLOCK_COLOR2_REG 0x0148
-#define TGA_BLOCK_COLOR3_REG 0x014c
-#define TGA_BLOCK_COLOR4_REG 0x0150
-#define TGA_BLOCK_COLOR5_REG 0x0154
-#define TGA_BLOCK_COLOR6_REG 0x0158
-#define TGA_BLOCK_COLOR7_REG 0x015c
-#define TGA_COPY64_SRC 0x0160
-#define TGA_COPY64_DST 0x0164
-#define TGA_CLOCK_REG 0x01e8
-#define TGA_RAMDAC_REG 0x01f0
-#define TGA_CMD_STAT_REG 0x01f8
-
-
-/*
- * Useful defines for managing the registers
- */
-
-#define TGA_HORIZ_ODD 0x80000000
-#define TGA_HORIZ_POLARITY 0x40000000
-#define TGA_HORIZ_ACT_MSB 0x30000000
-#define TGA_HORIZ_BP 0x0fe00000
-#define TGA_HORIZ_SYNC 0x001fc000
-#define TGA_HORIZ_FP 0x00007c00
-#define TGA_HORIZ_ACT_LSB 0x000001ff
-
-#define TGA_VERT_SE 0x80000000
-#define TGA_VERT_POLARITY 0x40000000
-#define TGA_VERT_RESERVED 0x30000000
-#define TGA_VERT_BP 0x0fc00000
-#define TGA_VERT_SYNC 0x003f0000
-#define TGA_VERT_FP 0x0000f800
-#define TGA_VERT_ACTIVE 0x000007ff
-
-#define TGA_VALID_VIDEO 0x01
-#define TGA_VALID_BLANK 0x02
-#define TGA_VALID_CURSOR 0x04
-
-#define TGA_MODE_SBM_8BPP 0x000
-#define TGA_MODE_SBM_24BPP 0x300
-
-#define TGA_MODE_SIMPLE 0x00
-#define TGA_MODE_SIMPLEZ 0x10
-#define TGA_MODE_OPAQUE_STIPPLE 0x01
-#define TGA_MODE_OPAQUE_FILL 0x21
-#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
-#define TGA_MODE_TRANSPARENT_FILL 0x23
-#define TGA_MODE_BLOCK_STIPPLE 0x0d
-#define TGA_MODE_BLOCK_FILL 0x2d
-#define TGA_MODE_COPY 0x07
-#define TGA_MODE_DMA_READ_COPY_ND 0x17
-#define TGA_MODE_DMA_READ_COPY_D 0x37
-#define TGA_MODE_DMA_WRITE_COPY 0x1f
-
-
-/*
- * Useful defines for managing the ICS1562 PLL clock
- */
-
-#define TGA_PLL_BASE_FREQ 14318 /* .18 */
-#define TGA_PLL_MAX_FREQ 230000
-
-
-/*
- * Useful defines for managing the BT485 on the 8-plane TGA
- */
-
-#define BT485_READ_BIT 0x01
-#define BT485_WRITE_BIT 0x00
-
-#define BT485_ADDR_PAL_WRITE 0x00
-#define BT485_DATA_PAL 0x02
-#define BT485_PIXEL_MASK 0x04
-#define BT485_ADDR_PAL_READ 0x06
-#define BT485_ADDR_CUR_WRITE 0x08
-#define BT485_DATA_CUR 0x0a
-#define BT485_CMD_0 0x0c
-#define BT485_ADDR_CUR_READ 0x0e
-#define BT485_CMD_1 0x10
-#define BT485_CMD_2 0x12
-#define BT485_STATUS 0x14
-#define BT485_CMD_3 0x14
-#define BT485_CUR_RAM 0x16
-#define BT485_CUR_LOW_X 0x18
-#define BT485_CUR_HIGH_X 0x1a
-#define BT485_CUR_LOW_Y 0x1c
-#define BT485_CUR_HIGH_Y 0x1e
-
-
-/*
- * Useful defines for managing the BT463 on the 24-plane TGAs
- */
-
-#define BT463_ADDR_LO 0x0
-#define BT463_ADDR_HI 0x1
-#define BT463_REG_ACC 0x2
-#define BT463_PALETTE 0x3
-
-#define BT463_CUR_CLR_0 0x0100
-#define BT463_CUR_CLR_1 0x0101
-
-#define BT463_CMD_REG_0 0x0201
-#define BT463_CMD_REG_1 0x0202
-#define BT463_CMD_REG_2 0x0203
-
-#define BT463_READ_MASK_0 0x0205
-#define BT463_READ_MASK_1 0x0206
-#define BT463_READ_MASK_2 0x0207
-#define BT463_READ_MASK_3 0x0208
-
-#define BT463_BLINK_MASK_0 0x0209
-#define BT463_BLINK_MASK_1 0x020a
-#define BT463_BLINK_MASK_2 0x020b
-#define BT463_BLINK_MASK_3 0x020c
-
-#define BT463_WINDOW_TYPE_BASE 0x0300
-
-/*
- * The framebuffer driver private data.
- */
-
-struct tga_par {
- /* PCI device. */
- struct pci_dev *pdev;
-
- /* Device dependent information. */
- void *tga_mem_base;
- void *tga_fb_base;
- void *tga_regs_base;
- u8 tga_type; /* TGA_TYPE_XXX */
- u8 tga_chip_rev; /* dc21030 revision */
-
- /* Remember blank mode. */
- u8 vesa_blanked;
-
- /* Define the video mode. */
- u32 xres, yres; /* resolution in pixels */
- u32 htimings; /* horizontal timing register */
- u32 vtimings; /* vertical timing register */
- u32 pll_freq; /* pixclock in mhz */
- u32 bits_per_pixel; /* bits per pixel */
- u32 sync_on_green; /* set if sync is on green */
-};
-
-
-/*
- * Macros for reading/writing TGA and RAMDAC registers
- */
-
-static inline void
-TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
-{
- writel(v, par->tga_regs_base +r);
-}
-
-static inline u32
-TGA_READ_REG(struct tga_par *par, u32 r)
-{
- return readl(par->tga_regs_base +r);
-}
-
-static inline void
-BT485_WRITE(struct tga_par *par, u8 v, u8 r)
-{
- TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
- TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
-}
-
-static inline void
-BT463_LOAD_ADDR(struct tga_par *par, u16 a)
-{
- TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
- TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
- TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
- TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
-}
-
-static inline void
-BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
-{
- BT463_LOAD_ADDR(par, a);
- TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
- TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
-}
-
-#endif /* TGAFB_H */
-
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