Re: 2.6.6-mm5
From: Eric W. Biederman (ebiederm_at_xmission.com)
Date: 05/24/04
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To: Andi Kleen <ak@muc.de> Date: 23 May 2004 18:02:50 -0600
Andi Kleen <ak@muc.de> writes:
> ebiederm@xmission.com (Eric W. Biederman) writes:
>
> > Currently I know of a safe version that will work on x86 on processors
> > with sse support. And I how to generate 64bit I/O cycles with using
> > mmx or x87 registers, but don't know if I can write code that touches
> > the FPU registers that is interrupt safe.
>
> As long as you save/restore cr0 and the FPU registers and do clts
> interrupts are not a problem. In fact interrupts are even easier that
> process context, where you need preempt_disable().
Thinking about this some more, I would need to transform every
preempt_disable() into a local_irq_disable() if I wanted to save
the FP registers to their home in struct task.
It looks to me like the only way to handle all of the x87 and mmx
subtleties is to call fsave which takes 108 bytes. That is a lot of
stack bytes to eat in irq context, and I suspect it is time consuming,
as well.
So I suspect it makes most sense just submit a patch for a sse version
of writeq on x86, and let the drivers that care use that. It does
mean that the drivers that care can't build for pre PentiumIII
hardware or must use a work around in generic kernels. So far the
cure for that looks much worse than the disease.
Eric
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- Previous message: Adrian Bunk: "[patch] John A. Martin no longer maintains the CREDITS file"
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