Re: [PATCH 2.6.13] lockless pagecache 2/7
From: Nick Piggin (nickpiggin_at_yahoo.com.au)
Date: 09/03/05
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Date: Sat, 03 Sep 2005 11:40:59 +1000 To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Alan Cox wrote:
>>but I suspect that SMP isn't supported on those CPUs without ll/sc,
>>and thus an atomic_cmpxchg could be emulated by disabling interrupts.
>
>
> It's obviously emulatable on any platform - the question is at what
> cost. For x86 it probably isn't a big problem as there are very very few
> people who need to build for 386 any more and there is already a big
> penalty for such chips.
>
>
Thanks Alan, Dave, others.
We'll see how things go. I'm fairly sure that for my usage it will
be a win even if it is costly. It is replacing an atomic_inc_return,
and a read_lock/read_unlock pair.
But if it does one day get merged, and proves to be very costly on
some architectures then we'll need to be careful about where it gets
used.
Nick
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