Re: [RFC] Secure Digital Host Controller PCI class

From: Pierre Ossman (drzeus-list_at_drzeus.cx)
Date: 11/22/05

  • Next message: Zwane Mwaikambo: "Re: 2.6.14.2 detects only one processor (out of 2)"
    Date:	Tue, 22 Nov 2005 07:07:18 +0100
    To: Greg KH <gregkh@suse.de>
    
    

    Greg KH wrote:

    >On Mon, Nov 21, 2005 at 12:45:40PM +0100, Pierre Ossman wrote:
    >
    >
    >>I'm working on a driver for the Secure Digital Host Controller
    >>interface. This is a generic interface, so it uses a PCI class for
    >>identification instead of vendor/device ids.
    >>
    >>The class ID used is 0805 and the programming interface (correct term?)
    >>indicates DMA capabilities. Greg, since you're the PCI maintainer,
    >>perhaps you have the possibility of checking this ID?
    >>
    >>
    >
    >What do you mean "checking this ID"? Checking it with what?
    >
    >
    >

    I figured you might have access to the official allocations from the PCI
    SIG.

    >>The standard also dictates a register at offset 0x40 in PCI space. This
    >>is a one byte register detailing the number of slots on the controller
    >>and the first BAR to use.
    >>
    >>
    >
    >Do you have a pointer to the standard?
    >
    >
    >

    The SDHC standard itself is a well guarded secret. We're basing this
    work on the little information that is out there and reverse engineering
    the Windows driver. The PCI registers are described in a spec. by Texas
    Instruments though:

    http://www-s.ti.com/sc/ds/pci6411.pdf

    They only use three bits for each field (since their controller only has
    three slots), but the Windows driver reads four so that is what I've put
    in the patch.

    Rgds
    Pierre

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