Re: [PATCH] Define wc_wmb, a write barrier for PCI write combining

On Sat, Feb 25, 2006 at 09:11:57AM -0800, Bryan O'Sullivan wrote:
On Sat, 2006-02-25 at 09:28 -0500, Benjamin LaHaise wrote:

sfence has no impact
on the flushing of the write combining buffers

The sfence instruction guarantees that every store that precedes it in
program order is globally visible, including over the likes of the PCI
bus, before any store instruction that follows the fence.

That is not the same as saying the write buffers are flushed and wholly
visible to their destination, it just means that subsequent reads or
writes will not be reordered prior to the sfence instruction. It is
entirely possible that the writes will remain in buffers on the CPU until
well after the sfence instruction has executed, sfence only affects the
order in which they become visible on the bus. If you want to force a
flush, a read from the PCI device is the only way to accomplish that.

-ben
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