Re: [RFC] MMIO accessors & barriers documentation


Frame buffers are rarely cachable as such, on x86 they are usually
write-combining. Which means that the writes can be merged and
possibly reordered while they are being written but they can't be
cached. Most arches I believe have something that roughly corresponds
to write combining.

Ensuring we can still use this optimization to mmio space is
moderately important.

I've not gone too much in details about write combining (we need to do
something about it but I don't want to mix problems) but I did define
that the ordered accessors aren't guaranteed to provide write combining
on storage mapped with WC enabled while the relaxed or non ordered ones
are. That should be enough at this point.

Later, we should look into providing an ioremap_wc() and possibly page
table flags for write combining userland mappings. Time to get rid of
MTRRs for graphics :) And infiniband-style stuff seems to want that too.

Ben.


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