Re: [patches] [patch 3/5] x86: Add PCI extended config space access for AMD Barcelona

On Mon, Sep 03, 2007 at 01:31:57AM -0700, Arjan van de Ven wrote:
On Mon, 03 Sep 2007 10:17:39 +0200
"Robert Richter" <robert.richter@xxxxxxx> wrote:

This patch implements PCI extended configuration space access for
AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
addresses. An x86 capability bit has been introduced that is set for
CPUs supporting PCI extended config space accesses.



No offence but this feels a bit wrong to me.

PCI is sort of more a chipset property than a cpu property (I realize
that this boundary is changing of course).

I'd like to ask you to at least rename some of the feature bits to
indicate that the extended config space is for the IO access method;
after all Linux already supports the MMIO method for accessing extended
config space since a really long time; not marking the feature bit to
indicate it's the IO method is going to be extremely confusing and
cause bugs I bet.

Hmm, yes the naming of the CPU capability bit seems wrong.
Guess, Robert will fix it.

(we probably need a global function that drivers can use to find out of
extended config space is accessible; however that for sure isn't a CPU
capability bit.

IMHO this is already available. Just check pci_dev->cfg_size which
is 256 if PCI ECS access is not possible (see pci_cfg_space_size()).

However the current naming etc sort of makes me fear
drivers will abuse this thing while thinking it's the right API)

Do you see any other issues besides the naming of the bit?


Regards,

Andreas

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