Re: RFC: outb 0x80 in inb_p, outb_p harmful on some modern AMD64 with MCP51 laptops

Rene Herman <rene.herman@xxxxxxxxxxxx> writes:

Alan, did you double-check that 8 us? I tried to but I seem to not
have trustworthy documentation.

I remember 16-bit CPU-driven ISA was able to do 2-3 MB/s transfers,
that means at least 1 Maccesses/second = up to 1 microsecond/access.

Perhaps IO ports accesses were slower than memory? But 8-12 times?
Perhaps port 0x80 was using (slower) 8-bit timings?

Bus-mastering ISA cards were able to do ca. 5 MB/s with 8 MHz (10 MHz?)
clocking, some old machines didn't like it.

Googling suggests that a slave access on 8-bit ISA bus was taking
6 cycles by default (including 4 wait states), 16-bit - 3 cycles
(with 1 WS). Respectively 0.75 us and 0.375 us, and 0.25 us for
16-bit 0WS memory access (with standard 8 MHz clock).

These values could be changed with BIOS setup, and devices could
use 0WS or I/O CHRDY signals if they didn't like the defaults
(dir 0WS mean 1 WS for 8-bit devices?).
--
Krzysztof Halasa
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