Re: [SLE] For or against ..Hyperthreading.

From: Dylan (dylan_at_dylan.me.uk)
Date: 08/31/03

  • Next message: Kastus: "Re: [SLE] Scripting"
    To: suse-linux-e@suse.com
    Date: Sun, 31 Aug 2003 22:26:18 +0100
    
    

    On Sunday 31 August 2003 21:52, Filipe Joel Almeida wrote:
    <SNIP>
    > What are the major benefits of a 64 bit processor over a 32 bit
    > processor?
    >
    > Let's say for mail or Database server... would there be significant
    > benefits from having a Dual Opteron over a Dual Xeon, and stuff like
    > that?
    >
    > Can anyone please shed some light on this subject?

    SFAIUI, assuming you are running a 64bit OS with apps compiled for 64bit, then
    there are several ways that the apparent speed may be improved:

    - with 64-bit internal registers, number crunching can operate directly on
    larger values, so maths-intensive processes can obviously benefit. The
    Opteron and Athlon-64 also have a different memory access archetecture so
    fetch and put operations are (supposed to be) more efficient.

    - 64-bit Address registers means more memory is directly addressable, meaning
    that larger files (or portions of them) can be kept in RAM at a time. This
    meand a database (for example) can potentially have a 'live' copy of an
    entire (set of) table(s) im memory, rather than paging sections to disk, and
    that swap may become effectively redundant. Also, larger memory blocks are
    directly accessible, meaning that block operations can be performed on larger
    blocks of memory. This would also speed up databases, and especially graphics
    and video apps.

    - 64-bit instruction registers opens up a whole magnitude of space for new CPU
    instructions (in principle if not yet in practice) to allow the processor to
    do a wider range of operations as primitive instructions (for example, fetch,
    shift-left, put could be a single opcode instead of three) or provide for
    sub-instructions or parameterised instructions. All this means less
    instructions would need to be fetched to perform the same ammount of work.

    The AMD chips are backwards compatible, so they will run existing OS's (albeit
    in 32-bit state), and 32 (or even 16) -bit apps on 64bit OS's natively. The
    Intel offering is NOT backwards compatible in that it requires a 64 OS, but
    can run 32-bit apps (under a 64-bit OS) in a mode which emulates a 32-bit
    Intel chip.

    I'm sure there's other benefits as well...

    Dylan

    -- 
    Sweet moderation
    Heart of this nation
    Desert us not
    We are between the wars
    - Billy Bragg
    -- 
    Check the headers for your unsubscription address
    For additional commands send e-mail to suse-linux-e-help@suse.com
    Also check the archives at http://lists.suse.com
    Please read the FAQs: suse-linux-e-faq@suse.com
    

  • Next message: Kastus: "Re: [SLE] Scripting"

    Relevant Pages

    • Re: speed it up
      ... can load many registers at once from memory and put many instructions ... the inner loop is unrolled ... The above loop tells the compiler that 4 registers ...
      (comp.lang.cpp)
    • Re: OT: IA-128 ???
      ... Would creating 128but floating point registers provide ... engine to store more of s database in memory to increase performance. ... Intel always pre-announces new technologies at IDF ... I'm sure everyone here already knew that some SSE2 instructions ...
      (comp.os.vms)
    • Re: PIC vs ARM assembler (no flamewar please)
      ... RISC features (such as 16 registers - a lot for its size). ... The 68k can handle both operands of an ALU instruction in memory, ... instructions that support sizes other than the native 32 bits are MOVEs. ...
      (comp.arch.embedded)
    • Re: OT: IA-128 ???
      ... Lets say they were to produce an 8086 with 64 bit addressing, ... Would creating 128but floating point registers provide ... engine to store more of s database in memory to increase performance. ...
      (comp.os.vms)
    • Re: ISA design styles
      ... between instructions, particularly about the pitfalls of such ... If you think of registers as a level in the memory hierarchy, ... is a storage to storage architecture. ...
      (comp.arch)