four Level Paging

From: "Dharma" <baladharma@xxxxxxxxx>
Date: 26 Mar 2007 22:22:25 -0700

Hi all,
I understood the paging design 0f 80386, we will have a PD
having 1024 entries, PT having 1024 entries and 12 bit offset.

But in Linux , we have PGD, PMD, PTE, Offset where, PGD can have 1024
entries, PMD is 1, PTE can have 1024, Offset will be 12 bit.

How is the above mapping mapped with the Processor. ?

Thanks a lot
Regards,
Dharma.

.

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