Re: intel x86 instruction "cli"

From: gopan (gop_kumar_at_hotmail.com)
Date: 03/19/04 

Date: 18 Mar 2004 22:38:23 -0800

>
> Then, does interrupt priority come into play here? When x86 issues 'cli'
> instruction due to interrupt 11, can interrupt 4 interrupt x86 again?
>
          The cli will cause processor to ignore all interrupts except
the NMI.

 The x86 processor when interrupted will clear the interrupt flag
until the ISR executiong completes, this basically means all
interrupts disabled.

 In linux the ISR will mask the corresponding interrupt bit in PIC and
will call sti so that processor can identify any new interrupt
generation ( as the interrupt
bit corresponding to the previous interrupt is cleared processor is
not notified
of the same interrupt again until ISR re enables that bit before
returning).

The purpose of this is to service any higher priority interrupts
arrival during the execution of current interrupt's ISR.

I had a similar doubt earlier and was cleared by the answers received
in this news group, hope I have understood correctly

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