Re: intel x86 instruction "cli"

From: Josef Möllers (josef.moellers_at_fujitsu-siemens.com)
Date: 03/19/04 

Date: Fri, 19 Mar 2004 09:41:20 +0100

tcs wrote:
>> OK, here is my question. When x86 executes "cli" instruction, does CPU
>>itself ignore the interrupt or the interrupt controller screen the
>
> interrupt
>
>>from arriving CPU?
>
>
> The CPU ignores the interrupt. You can still detect a pending interrupt
> by polling the interrupt controller.
>
> Then, does interrupt priority come into play here? When x86 issues 'cli'
> instruction due to interrupt 11, can interrupt 4 interrupt x86 again?
>
> We are asking this because we would like to know if interrupt 4 can
> interrupt handler for interrupt 11?

gopan has already answered some of this.

1. cli will mask _all_ maskable interrupts.
2. with the PIC and APIC used in x86 systems, the OS can mask some
interrupt sources within the PIC, masked interrupts will not make it
past the (A)PIC.
3. (A)PICs support some form of priorization or another. IIRC, the 8259
PIC will allow for rotating priorities, i.e. once IRQ 11 has been
recognized, it will rotate into the least priority and, if IRQ 11 and
IRQ 4 will happen before the CPU can act upon either, the PIC will
report IRQ 4 as the one with the highest priority. The APIC allows for
static priorities IIRC.
4. "Interrupts through interrupt gates automatically clear the IF flag,
which disables interrupts."

In general, you should not have to worry about interrupts occurring
during interrupt handlers: the (A)PIC or the device itself will prevent
an interrupt from happening during its own interrupt handler. Also
interrupt handlers must be written such that the will not interfere with
other pieces of code or both must protect from each other. If you are
within a critical section of code (i.e. you must proceed at maximum
speed), you must disable interrupts. 

-- 
Josef Möllers (Pinguinpfleger bei FSC)
	If failure had no penalty success would not be a prize
						-- T.  Pratchett

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