Re: intel x86 instruction "cli"
From: news (me_at_privacy.net)
Date: 03/19/04
- Previous message: Josef Möllers: "Re: intel x86 instruction "cli""
- In reply to: gopan: "Re: intel x86 instruction "cli""
- Next in thread: Kasper Dupont: "Re: intel x86 instruction "cli""
- Reply: Kasper Dupont: "Re: intel x86 instruction "cli""
- Reply: Ed Skinner: "Re: intel x86 instruction "cli""
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
Date: Fri, 19 Mar 2004 09:55:45 +0100
> In linux the ISR will mask the corresponding interrupt bit in PIC and
> will call sti so that processor can identify any new interrupt
> generation ( as the interrupt
> bit corresponding to the previous interrupt is cleared processor is
> not notified
> of the same interrupt again until ISR re enables that bit before
> returning).
I have a question on this. Why is the line masked, given that the
hardware will not generate another int until it is serviced?
Why not just only acknowledge the PIC?
> The purpose of this is to service any higher priority interrupts
> arrival during the execution of current interrupt's ISR.
But if ints are enabled, lower priority interrupts could be
triggered too, right?
- Previous message: Josef Möllers: "Re: intel x86 instruction "cli""
- In reply to: gopan: "Re: intel x86 instruction "cli""
- Next in thread: Kasper Dupont: "Re: intel x86 instruction "cli""
- Reply: Kasper Dupont: "Re: intel x86 instruction "cli""
- Reply: Ed Skinner: "Re: intel x86 instruction "cli""
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
Relevant Pages
|