Re: Is disabling the cache required for DMA
From: gopan (gop_kumar_at_hotmail.com)
Date: 10 Nov 2004 21:21:26 -0800
Josef Moellers <firstname.lastname@example.org> wrote in message news:<email@example.com>...
> x86 processors use a technique called "bus snooping", i.e. they check
> all accesses to physical memory.
> When a DMA write (i.e. a DMA transfer from the IO device into memory)
> occurs to an address which is held in the cache, the cache line is
> automatically made invalid.
> Likewise, when a DMA read occurs to an address which is held in a cache
> and is dirty and the cache policy is "write back", then the processor
> (i.e. the cache control logic) will detect this and will supply the data.
Thanks a lot ! that really cleared my doubts about x86 DMA handling !!