Re: mem mapped I/O
From: Josef Moellers (josef.moellers_at_fujitsu-siemens.com)
Date: 01/18/05
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Date: Tue, 18 Jan 2005 08:50:04 +0100
guruteck@gmail.com wrote:
> Hi
>
> In Mem Mapped I/O a part of device memory and registers are mapped in
> to RAM.If we do any operation on them are immediately visible to
> device.
> My question is When it will be visible to device.Immediately after
> writing in to RAM??
There is no "writing to RAM", there is either RAM or a device.
> Or device memory is flushed in some regular intervals, only after that
> it will be visible for device..
It all depends on whether there is a cache of some sorts between the CPU
and the device.
If there is no cache, any store operation will immediately be reflected
by changes in the state of the hardware.
If there is a cache (and/or a "write buffer"), then this cache or buffer
must be flushed or the cache line must be replaced before a change in
the state happens. Note that a cache will most likely not adhere to byte
or word accesses but will use the largest width possible, so in any
case, caching must be switched off. If there is a "write buffer" which
cannot be switched off (there used to be one on MIPS RISC systems), this
must be flushed explicitly.
Then there is the internal operation of the device. If you store some
information in device-memory, the exact sequence of events depends on
the architecture of the device. Most likely, the device will not really
notice any writes to its memory until a device register is written e.g.
to transmit a pointer, offset or index to the device. Having
device-memory allows the device to access the memory faster that it can
access main memory and the interface from the device to its memory can
be kept simpler (1MB of device-memory requires 20 address lines, 1MB of
memory-mapped buffer in a 4GB physical address space requires 32 address
lines, also no PCI addressing is required).
HTH,
Josef
-- Josef Möllers (Pinguinpfleger bei FSC) If failure had no penalty success would not be a prize -- T. Pratchett
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