Re: why inter-changing pci slot works?

"David Schwartz" <davids@xxxxxxxxxxxxx> writes:
phil-news-nospam@xxxxxxxx wrote:

It's definitely (still) time for a whole new computer I/O architecture
design that does not involve interrupt identification separate from the
device identity. The original IRQ was supposed to be a priority level
on a very small machine with few devices. That's just a mess for today's
needs. What we need is a machine with each device having a unique ID
that spells out both it's memory address range as well as it's interrupt
ID (being the same ID). Maybe that would be an ID bound to a slot or
maybe it would be settable on the boards. The OS can then map those
devices as needed.

I believe this is precisely what MSI does (message signaled
interrupts).

Not quite (actually, not at all ;-). A traditional PCI device has up
to four interrupt pins (A, B, C, D) and uses them to signal interrupts
to the host as level-triggered active low. This means they can be
shared easily, because there is no risk to 'lose' and interrupt while
serving another (the pin of each device currently signalling an
interrupt will remain low until reset by host software). But the
'messy' part comes after that: A system typically has an interrupt
controller of some nature (and traditional PCs are exceptionally
grotty in this respect) which aggegrates interrupt inputs from a
number of different source (like PCI IRQ pins) and is cable of
actually interrupting the host CPU. If this happens, host software
must read some kind of status register to determine which set of
sources are currently interrupting (typically represented as bitmap
with the position of a bit in this bitmap being the IRQ number) and
demultiplex the input event set to a set of device drivers.

The interrupt controller can support only a limited amount of
different interrupt sources. On system startup, host software
enumerates the present PCI devices and assigns interrupt numbers to
them 'somehow' (eg on our newer hardware, the core does not provide a
'direct' connection between PCI IRQ inputs and the interrupt
controller, so the respective pins need to be connected to available
GPIO pins of the core, which, in turn, can functions as inputs to the
interrupt controller). The assigned interrupt numbers are stored in the
'interrupt line register' in the PCI configuration space of each
device and the device drivers are supposed to read them from there and
to inform the host operating system that driver soandso should be
'activated' if IRQ #n is active. The driver is supposed to determine
if it was 'his' device that interrupted and if it was, do something to
make the interrupt condition disappear on this device. Afterwards, if
the condition persists, the next driver that registered itself for the
IRQ number in question is activated and so on.

The difference between MSI and traditional PCI IRQs is that, instead
of being delivered as out-of-band signal using dedicated circuitry,
an interrupt condition is signalled by doing an inbound (from device
to host) memory write over the PCI to a specific
address. Responsibility for assigning unique addresses to each device
rests with the host software. But this transports the interrupt event
only to the PCI controller (or whatever component feels itself
addressed at this area of the physical memory map). There still needs
to be some kind of 'interrupt controller' that can actually interrupt
the CPU, with IRQ numbers that may be shared etc pp, meaning, while
this is supposedly cheaper (less pins) it doesn't adresss the 'messy'
part at all. And it isn't even theoretically real-time capable.
.

Relevant Pages

  • ACPI IRQ routing problems with Thinkpad T40
    ... I'm running 2.6.3 with ACPI ... assigned IRQ 9, but it generates interrupts on IRQ 5. ... while the kernel disables IRQ 5 as nobody is handling the interrupt. ... PCI: PCI BIOS revision 2.10 entry at 0xfd8d6, ...
    (Linux-Kernel)
  • Re: can someone explain...[ PCI interrupts]
    ... interrupts for PCI devices are roughly split up into two categories: INTx interrupt lines and MSI interrupts. ... Each processor contains a local APIC that can receive messages from other APICs and send messages to other local APICs. ... Basically, an IRQ value is a cookie useful for binding a device interrupt tuple or an ISA IRQ) to a x86 interrupt tuple. ...
    (freebsd-current)
  • Re: wont work: 2.6.0 && SiI 3112 SATA
    ... PCI: PCI BIOS revision 2.10 entry at 0xf0031, ... PCI: Found IRQ 10 for device 0000:00:1f.1 ... hde: lost interrupt ...
    (Linux-Kernel)
  • Re: x86, shared IRQ. how to track down the culprit?
    ... IRQ20 is being shared by drivers with different interrupt levels. ... The vector value is the IRQ assigned, and you will probably find two entries ... It means the BIOS has assigned two PCI devices the same IRQ ...
    (comp.unix.solaris)
  • Re: can someone explain...[ PCI interrupts]
    ... interrupts for PCI devices are roughly split up into two categories: INTx interrupt lines and MSI interrupts. ... Each processor contains a local APIC that can receive messages from other APICs and send messages to other local APICs. ... Basically, an IRQ value is a cookie useful for binding a device interrupt tuple or an ISA IRQ) to a x86 interrupt tuple. ...
    (freebsd-current)