Re: Kernel code and processor's Cache

David Schwartz <davids@xxxxxxxxxxxxx> writes:
On Apr 11, 2:55 pm, Phil Carmody <thefatphil_demun...@xxxxxxxxxxx>
wrote:

David Schwartz <dav...@xxxxxxxxxxxxx> writes:

Sometimes, but not always. Consider a page fault for an mmap'ed file.

But that would be mapped into the user address space, and wouldn't
be cached in the kernel-specific cache?

That page would *also* be mapped into user address space (with one or
more additional mappings), but so what? How would the cache logic know
whether the next access was going to come from the kernel or user
space.

How does cache logic know if the next read from a page will be an
instruction fetch or a data read? There's nothing new about having
multiple different caches for different purposes on a system.

Phil
--
I find the easiest thing to do is to k/f myself and just troll away
-- David Melville on r.a.s.f1
.

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