GPIO twiddling on the i440MX (i82443MX) ???

From: google (google_at_losdos.dyndns.org)
Date: 07/10/04

  • Next message: Uday Mullangi: "timers" 
    Date: 10 Jul 2004 00:41:19 -0700

    hi,
    i am working with a 440MX-based embedded system -- specifically,
    it uses the Intel 82443MX integrated north/south device ("Banister").

    i would like to be able to toggle the GPIO pins from a userland
    application running under linux (2.4 kernel). i.e., i need to
    toggle GPIO1 (pin E4) through GPIO20 (pin K3).

    according to the 440MX/82443 data*** and application programming
    guides, the GPIO pins are accessible through PCI config function 0,
    registers B0-B3, D4-DB, and E0-E3. this is from section 6-15 of
    http://developer.intel.com/design/chipsets/datashts/24529201.pdf

    my question is, how do i access the PCI registers from userland C?
    i have seen some examples using inb/outb but for the most part they
    are geared towards addressing the parallel port. i can look up the
    exact register values for the 440MX, that's not the problem -- the
    question is how does one implement userland-to-PCI-space read/write
    routines using the linux inb/outb primitives?

    additionally, i understand some measures need to be taken to allow
    a userland application to write directly to PCI memory (ostensibly
    bypassing memory bounds checking). can anyone suggest some links
    which demonstrate how this is implemented as well?

    any pointers appreciated.

    thanks and regards,
    jim

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