Re: Embedded linux: With or without MMU



Xenu The Enturbulator wrote:
Michael Schnell wrote:

(Besides the potential difference in hardware execution speed) With any task switch the OS has to do some work to reprogram the MMU (and with ARM the cache gets invalidated).

Are you sure about this ? If it were true, the performance would completely suck. Remember, ARM was originally designed for desktop use as well, AFAIK .. wasn't it used in those Acorn Archimedes machines ?

The first ARM was for the Acorn Archimedes machines, but it did not have an MMU, and I'm not sure that it even had a cache (it ran at 8 MHz IIRC, and in those days memory was not much slower than cpus).

There are two ways to handle cache and MMU - you can cache by physical address (which causes slower access to the cached data, as addresses need to be translated before accessing the cache), or you can cache by virtual address (which is faster for the cpu to access as the logical addresses are used directly, but it requires a cache flush when changing the MMU maps).

I don't know which method the ARM uses. I've a vague feeling that on larger processors, L1 caches use virtual addresses while L2 (and L3) use physical addresses, but that could be wrong.
.



Relevant Pages

  • Good document on ARM cache policies w.r.t. timing?
    ... I don't mind groveling through the ARM ARM and working it out from ... entries in the TLBs so the MMU doesn't have to touch RAM to look them ... How to lock code into cache? ... Is a cache line fill aligned on a hard ...
    (comp.arch.embedded)
  • Re: Exploring Windows CE Shellcode
    ... > well xscale to be exact but thats arm v5 IIRC. ... > similar problems in your WinCE shellcode? ... Tim is flushing the cache using the following instruction: ...
    (Pen-Test)
  • Re: [PATCH 1/2] DMA buffer alignment annotations
    ... platforms that do not have coherent caches. ... as ARM, MIPS, etc... ... To get this macro, architectures have ... +share a cache line with any other data. ...
    (Linux-Kernel)
  • Re: Locking data and instruction cachelines
    ... I'm using an Intel PXA270 based ARM variant, and I noticed that the article about locking cache lines on ARM's web site seemed to indicate that one can only lock instruction cache lines on ...
    (comp.sys.arm)
  • Re: Good document on ARM cache policies w.r.t. timing?
    ... I don't mind groveling through the ARM ARM and working it out from ... How to lock code into cache? ... Is a cache line fill aligned on a hard ... I somewhere had a document going into this in some detail and a doc from Broadcom looking at it for the parts I used (MIPS core based) because it impacted the internal bus significantly. ...
    (comp.arch.embedded)