Re: what is IRQ sharing?

On Thu, 22 Feb 2007, in the Usenet newsgroup comp.os.linux.hardware, in article
<slrnetruci.5dq.john@xxxxxxxxxxxxxxxxxx>, John Thompson wrote:

On the common PC (x86) processors, hardware devices can use special
signals called "interrupt requests" (aka IRQ) to tell the cpu they need
some attention. x86 type processors allow up to 16 interrupts, but
several of these are reserved for specific devices such as the system
timer, keyboard, and real-time clock.

That's the hardware implementation - an artifact of the design used by
IBM on the PC family. The x86 processor has only three pins for
external interrupts - "RESET" (which is the 'power on start' function
and _may_ also have a front panel push button), NMI (which _was_ used
by the original IBM designs for a memory parity error - less common
today) and "INTR" (the maskable interrupt). When the "INTR" interrupt
is asserted, the CPU generates an INTA cycle, and reads the low eight
bits of the data bus as an interrupt identification - 8 bits allowing
for 256 different interrupts. The original IBM PC design used an
8259 priority encoder chip to generate the INTR - and this allowed
for only 8 interrupts (IRQ lines). The PC-AT added a second 8259 chip
cascading into the first allowing for 15 interrupts (IRQ2 being stolen
for the cascade function, and the former IRQ2 being connected to IRQ9).
Only the low 4 bits of the data bus were connected to the 8259s. Since
roughly the introduction of the 80486, the function of the 8259 chips
have been integrated into the motherboard chipset (now part of the
Southbridge chip).

Another (IRQ2) is dedicated to providing a cascade to a second IRQ
controller -- this is a legacy of the original 8086 processor design
which only allowed for 8 interrupts. IRQ2 cascades to a second
controller which provides another 8 interrupts for a total of 16.

You're confusing the hardware implementation with the CPU - which was
quite different. See any of the data manuals for an x86 processor from
Intel, Cryix, IBM, or AMD among others.

Even this cobble-job was only helpful for a while; as people added more
devices (sound cards, addition HD controllers, network cards, video
cards, etc) all requiring their own IRQ it quickly became a nightmare
to manage all this.

Again - a hardware limitation. The ISA bus didn't have all of the IRQ
pins on the card connector. The original 8 bit socket had IRQ 2
through 7. The 16 bit socket renamed IRQ2 to IRQ 9, and added IRQ 10,
11, 12, 14 and 15 (13 was reserved for the match co-processor chip).
The 32 bit connectors (EISA, MCA, and VESA) didn't alter this. The PCI
and AGP socket only has four interrupt pins (INTA, INTB, INTC, and INTD),
and how these are connected to the Southbridge is very implementation
specific - with the BIOS setup confusing things further. GENERALLY,
the designs have the same four IRQs used by the four interrupt pins,
so if you have more than four PCI slots (or 4 PCI sockets and a AGP
socket and/or USB controller, which also uses the PCI bus), there will
be two or more PCI type devices sharing an IRQ.

Part of the problem is that IRQs have traditional uses. IRQ 0 is the
system timer (used to keep track of relative time), and IRQ 1 is the
keyboard. BEYOND this, things are slightly less 'cast in stone'. IRQ 6
is normally the floppy controller, IRQ 12 is the PS/2 interface, IRQ 13
as noted above is the FPU (even though this is now normally part of the
CPU), and IRQ 14 and 15 are the IDE controller. Beyond this, it's wide
open, though IRQ 10 is often the network card, IRQ 12 the primary SCSI
controller, IRQ 5 either video or CD drive, and IRQ 3 and 4 for the
RS-232 style serial ports.

When the PCI bus was designed in the mid 80s

The PCI specification was only released in June 1992, and revised in
1993 and 1995.

Old guy

.

Quantcast