Re: Applying Intel IA32 Microcode Update [OK]
From: Bob Hauck (postmaster_at_localhost.localdomain)
Date: 10/28/03
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Date: Tue, 28 Oct 2003 20:07:09 GMT
On 28 Oct 2003 02:55:57 -0800, Neil Zanella <nzanella@cs.mun.ca> wrote:
> Bob Hauck <postmaster@localhost.localdomain> wrote in message
>> Presumably because the CPU stores the microcode in volatile storage.
> Interesting, but where exactly is this non-volatile storage?
You mean the volatile storage? Inside the CPU, I presume. I do not
know how it is accessed, never having looked into it. It does seem to
be volatile though, what with it having to be re-loaded on each boot.
> Also, why would the OS need to reload such microcode if the BIOS already
> loads it from its 4 megs or so of nonvolatile storage?
Maybe the OS has a newer version. People upgrade the OS a lot more
often than the BIOS.
>> There are many types of FPGA's that are volatile.
> These devices use ordinary main memory technology instead of EPROM
> technology?
The device sort of acts like a static RAM. It will remember the
configuration as long as there is power. I do not know all the details
of how they are implemented internally.
Basically FPGA design tools output a file that represents a stream of
bits to be loaded into the device to configure it as desired. There are
various ways of loading this file into the device. Some devices then
remember it forever, like an EEPROM or Flash device, others don't.
I presume that part of Intel's CPU has some kind of programmable logic
that is configured by these microcode updates. There's no reason that
has to be non-volatile. Non-volatile storage typically consumes more
space on the die and has a limited life.
> I can't see that standalone volatile FPGAs would have that many real life
> applications.
They are used a lot. As I said, Xilinx sells dozens of different kinds,
as do Altera and others.
> So how is volatile memory useful for FPGAs in real life situations. Is
> it used mainly for prototyping? If so, then a simulator would do just
> as well.
There are several ways to use them. There are typically some pins that
you can ground or tie to Vcc to tell the device how to get its data.
One mode is to have a separate serial EEPROM that the device loads from,
another is to have a CPU on the board load it. IOW, there has to be
some non-volatile storage somewhere, just not necessarily in the FPGA
itself.
There are many reasons why this is useful. For one thing, it is easier
for end-users to pull an 8-pin DIP off the board than a 144-pin PQFP.
Your customers also normally won't have a JTAG pod handy so they can't
program it that way. From the standpoint of doing field upgrades it
makes sense. You just pop a new serial EEPROM into a socket.
Another reason is in-system programmability. A project I'm working on
right now uses an FPGA to do various kinds of data conversion. It
currently has (it will grow) three different loads for the FPGA. The
CPU decides which one to use depending on what setup the user selects.
IOW, we change the FPGA programming on they fly while the system is
running.
This allows us to have a much smaller and less expensive FPGA than would
be required to support all functions at once. The CPU of course boots
from a flash that has both the software and the FPGA code in it but
flash space is a lot cheaper than FPGA gates. Another benefit of doing
it this way is that we can upgrade both the software and the FPGA by
uploading to a serial port.
-- -| Bob Hauck -| To Whom You Are Speaking -| http://www.haucks.org/
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