Makefile dependency problem

dirty.harry_at_juno.com
Date: 09/29/05


Date: 29 Sep 2005 08:09:34 -0700


Lets say that I have source code file, foo.c, that directly includes
header files a.h and b.h. Further, suppose a.h, include aa.h and
similarly, b.h includes bb.h. I would like to set up a Makefile so
that if aa.h or bb.h is modified, foo.c is compiled. However, I would
like to do it by saying that foo.c depends upon a.h and b.h, and that
a.h "depends" upon aa.h, and that b.h "depends" upon bb.h. Note that
on the last two I put depends in "" since a.h and b.h don't really need
to be updated.

I would like to do something similar to:

foo.o: a.h b.h
         compile foo.c

a.h: aa.h
       do something

b.h: bb.h
      do something

Thus if bb.h is modified, foo.c gets recompiled. At the moment I can
have the "do something" be "touch b.h" which will make foo.c get
recompile. However, since b.h is not really changed, I would really
not prefer not to force a time stamp change on the file in the manner.

Obvisously, I could also do something like

foo.o: a.h b.h aa.h bb.h

but suppose I have many other source files with similar dependencies.
(Yes I know about makedepend but it puts in a lot of system file
headers even with the -Y flag which I don't want in the file)

So I'm looking for a way for a dependency to force another dependency
without modifying the time-stamp of the file that occurs between the
two.



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