Re: How to write a kernel patch to expose a kernel-level function?


Jean-David Beyer wrote:
> Peter T. Breuer wrote:
> > John Hasler <john@xxxxxxxxxx> wrote:
> >> hzmonte writes:
> >>> What I want, and what smp_processor_id() returns, is which logical
> >>> processor the calling thread is running on. Is CPU0, CPU1, or CPU2, for
> >>> example?
> >
> >> Why? Of what possible use could that information be? What problem are you
> >> trying to solve?
> >
> > Dunno. Probably some mistaken idea. But anyway it would be simple to do
> > - some ioctl which returns what he wants. But doesn't he have the info
> > in proc anyway?
> >
> How would that do any good? When the process makes the kernel call on ioctl,
> a process switch will occur and what would the ioctl return? The
> processor-id that the process _used to_ run on, not the one it will run on
> once the ioctl returns.
>
> He is doomed. The only way I can think of that will work is to examine the
> code of the kernel in the area where process switching occurs. I looked in
> there a while ago, and it really tries to return a process to the same
> processor it ran on before to try to maintain a high cache hit ratio, but
> with the puny caches on my processors (1 Megabit L3 caches) compared to
> process sizes (50Megabytes and up for some of the large ones), this may be
> of only minor importance.
>
> It depends on the working set size of all the processes currently running. I
> have a dbms that runs many processes, and does a lot of IO. Runs pretty well
> unless I let BOINC run 4 compute-limited processes at nice 19. Running BOINC
> this way should take up all the otherwise unused CPU cycles and not
> interfere with the higher priority processes, but it spoils the database
> application(s). They try to do a disk write and suspend. Then a BOINC
> process runs and dirtys up the caches, so when the IO for the dbms completes
> and the dbms process resumes, the cache is completely dirty so it runs at
> RAM speeds (533MHz) instead of processor speeds (3.06GHz).

Isn't some of this info the OP desires (considering HT, and/or Dual
Core CPUs) highly dependent upon "which" brand (Intel or AMD64) the OP
is using ??

I'm not up on this at all - and I don't yet have a great grasp on
explaining the technology and functions , but doesn't AMD64 incorporate
_NUMA_, the HTT Bus, and the A64 Memory Controller is OnDie, ["MOESI
protocol" (Modified, Owned, Exclusive, Shared, Invalid)] since their ,
as oppposed to the Intel Architecture (Xeon, Pentium-D, and HT -- I'm
don't know about Itanium though).
<http://en.wikipedia.org/wiki/Non-Uniform_Memory_Access>
more info about the diffs;
<http://www.xbitlabs.com/articles/cpu/print/dual-core.html>

hmmm..wonder how MShafts PAE crap figures into all this too ?

.

Relevant Pages

  • Re: How to write a kernel patch to expose a kernel-level function?
    ... When the process makes the kernel call on ioctl, ... with the puny caches on my processors compared to ... have a dbms that runs many processes, and does a lot of IO. ... unless I let BOINC run 4 compute-limited processes at nice 19. ...
    (comp.os.linux.misc)
  • Re: How to write a kernel patch to expose a kernel-level function?
    ... But anyway it would be simple to do>> - some ioctl which returns what he wants. ... There is no special extra process switch on ioctl - he'll get whatever cpu is running his ioctl. ... Yes, it is another question if the kernel decided to switch him to a different cpu on the i/o, but his chances of that are low, or at least about as low as with anything he does if there is any affinity at all. ... I looked in> there a while ago, and it really tries to return a process to the same> processor it ran on before to try to maintain a high cache hit ratio, but> with the puny caches on my processors compared to> process sizes, this may be> of only minor importance. ...
    (comp.os.linux.misc)