"Indirect Configuration" of Intel 21555 P2P Bridge

From: W Travis (wct2003jm_at_comcast.net)
Date: 01/30/04 

Date: 30 Jan 2004 13:54:46 -0800

I am working with a client that is developing an intelligent PCI
adapter employing the Intel 21555 Non-transparent PCI bridge. They
have elected to not employ a serial ROM preload, and their local
processor is not ready for prime time. For the short term, I am as a
result trying to employ the "indirect configuration" briefly mentioned
in section 6.3.4 of the July 2001 Intel guide (Intel 278321-002). I am
unclear on the nature of the transactions that the bridge requires to
act upon its own registers, mocking the configuration actions the
local processor would normally perform.

If you have advice, know of an example of this in code somewhere,
anything - I would be grateful. The goal is to load the BARs, their
CSRs, and touch a few other 'local/secondary-only write" registers
without enlisting upon the local (adapter) processor.

The client's prototype hs properly strapped pr_ad[3] down to override
the primary lockout. Linux (or perhaps stray activity on the local
processor side) brings the 21555 up with a very suspect BAR0 for
memory (address 0xe490 0000), and Linux maps the BAR1 for IO into a
nice proper range. I ensure that the Downstream Transaction Enable is
set, then attempt Type 1 transactions via the Downstream Transaction
Address and Data registers using I/O access (via BAR1). I am seeing no
valid responses in my efforts to probe the downstream/local bus,hence
I am asking for input here. I'm looking into Type 0 concerns (idsel)
on the adapter now as well as lookijg through LInux trying to see
where/how it manages to configure the BARs (0 and 1).

Thanks!